View F25L004A-100PG_5824991.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 1/32 4mbit (512kx8) 3v only serial flash memory ? features y single supply voltage 2.7~3.6v y speed - read max frequency : 33mhz - fast read max frequency : 50mhz; 75mhz; 100mhz y low power consumption - typical active current - 15 a typical standby current y reliability - 100,000 typical program/erase cycles - 20 years data retention y program - byte program time 7 s(typical) y erase - chip erase time 4s(typical) - sector erase time 60ms(typical), y auto address increment (aai) word programming - decrease total chip programming time over byte-program operations y spi serial interface - spi compatible : mode 0 and mode3 y end of program or erase detection y write protect ( wp ) y hold pin ( hold ) y package available - 8-pin soic 150-mil - 8-pin soic 200-mil block erase time 1sec (typical) ordering information part no. speed package comments f25l004a -50pg 50mhz 8 lead soic 150 mil pb-free f25l004a -100pg 100mhz 8 lead soic 150 mil pb-free f25l004a -50pag 50mhz 8 lead soic 200 mil pb-free part no. speed package comments f25l004a ?100pag 100mhz 8 lead soic 200 mil pb-free f25l004a ?50dg 50mhz 8 lead pdip 300 mil pb-free f25l004a ?100dg 100mhz 8 lead pdip 300 mil pb-free general description the f25l004a is a 4megablt, 3v only cmos serial flash memory device organized as 512k bytes of 8 bits. this device is packaged in 8-lead soic 200mil. esmt?s memory devices reliably store memory data even after 100,000 program and erase cycles. the f25l004a features a sector erase architecture. the device memory array is divided into 128 uniform sectors with 4k byte each ; 8 uniform blocks with 64k byte each. sectors can be erased individually without affecting the data in other sectors. blocks can be erased individually without affecting the data in other blocks. whole chip erase ca pabilities provide the flexibility to revise the data in the device. the sector protect/unprotect feat ure disables both program and erase operations in any combin ation of the sectors of the memory.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 2/32 pin configurations 8-pin soic 8-pin pdip 0 1 8 2 7 3 6 4 5 vdd hold sck si ce so wp vss 1 8 2 7 3 6 4 5 vdd hold sck si ce so wp vss
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 3/32 pin description symbol pin name functions sck serial clock to provide the timing for serial input and output operations si serial data input to transfer commands, addresses or data serially into the device. data is latched on the rising edge of sck. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of sck. ce chip enable to activate the device when ce is low. wp write protect the write protect ( wp ) pin is used to enable/disable bpl bit in the status register. hold hold to temporality stop serial communication with spi flash memory without resetting the device. vdd power supply to provide power. vss ground
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 4/32 sector structure table1 : f25l004a sector address table block address block sector sector size (kbytes) address range a18 a17 a16 127 4kb 07f000h ? 07ffffh : : : 7 112 4kb 070000h ? 070fffh 1 1 1 111 4kb 06f000h ? 06ffffh : : : 6 96 4kb 060000h ? 060fffh 1 1 0 95 4kb 05f000h ? 05ffffh : : : 5 80 4kb 050000h ? 050fffh 1 0 1 79 4kb 04f000h ? 04ffffh : : : 4 64 4kb 040000h ? 040fffh 1 0 0 63 4kb 03f000h ? 03ffffh : : : 3 48 4kb 030000h ? 030fffh 0 1 1 47 4kb 02f000h ? 02ffffh : : : 2 32 4kb 020000h ? 020fffh 0 1 0 31 4kb 01f000h ? 01ffffh : : : 1 16 4kb 010000h ? 010fffh 0 0 1 15 4kb 00f000h ? 00ffffh : : : 0 0 4kb 000000h ? 000fffh 0 0 0
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 5/32 table2 : f25l004a block protection table top status register bit protected memory area protection level bp2 bp1 bp0 block range address range 0 0 0 0 none none upper 1/8 0 0 1 block 7 70000h ? 7ffffh upper 1/4 0 1 0 block 6~7 60000h ? 7ffffh upper 1/2 0 1 1 block 4~7 40000h ? 7ffffh all blocks 1 0 0 blo ck 0~7 00000h ? 7ffffh all blocks 1 0 1 blo ck 0~7 00000h ? 7ffffh all blocks 1 1 0 blo ck 0~7 00000h ? 7ffffh all blocks 1 1 1 blo ck 0~7 00000h ? 7ffffh bottom status register bit protected memory area protection level bp2 bp1 bp0 block range address range 0 0 0 0 none none bottom 1/8 0 0 1 block 0 00000h ? 0ffffh bottom 1/4 0 1 0 block 0~1 00000h ? 1ffffh bottom 1/2 0 1 1 block 0~3 00000h ? 3ffffh all blocks 1 0 0 blo ck 0~7 00000h ? 7ffffh all blocks 1 0 1 blo ck 0~7 00000h ? 7ffffh all blocks 1 1 0 blo ck 0~7 00000h ? 7ffffh all blocks 1 1 1 blo ck 0~7 00000h ? 7ffffh block protection (bp2, bp1, bp0) the block-protection (bp2, bp1, bp0) bits define the size of the memory area, as defined in table2 to be software protected against any memory write (progr am or erase) operations. the write-status-register (wrsr) inst ruction is used to program the bp2, p1, bp0 bits as long as wp is high or the block-protection-look (bpl) bit is 0. chip-erase can only be executed if block-protection bits are all 0. after power-up, bp2, bp1 and bp0 are set to1. block protection lock-down (bpl) wp pin driven low (v il ), enables the block-protection -lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp2, bp1, and bp0 bits. when the wp pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to 0.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 6/32 funtional block diagram address buffers and latches x-decoder flash y-decoder i/o butters and data latches serial interface control logic ce sck si wp so hold
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 7/32 hold operation hold pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold mode, ce must be in active low state. the hold mode begins when the sck active low state coincides with the falling edge of the hold signal. the hold mode ends when the hold signal?s rising edge coincides with the sck active low state. if the falling edge of the hold signal does not coincide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reac hes the active low state. see figure 1 for hold condition waveform. once the device enters hold mode, so will be in high impedance state while si and sck can be v il or v ih . if ce is driven active high during a hold condition, it resets the internal logic of the device. as long as hold signal is low, the memory remains in the hold condition. to resume communication with the device, hold must be driven active high, and ce must be driven active low. see figure 18 for hold timing. active hold active hold active hold sck figure 1 : hold condition waveform write protection f25l004a provides software write protection. the write protect pin ( wp ) enables or disables the lockdown function of the status register. the block-protection bits (bp1, bp0, and bpl) in the status regist er provide write protection to the memory array and the status register. see table 5 for block-protection description. write protect pin ( wp ) the write protect ( wp ) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp is driven low, the execution of the wr ite-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 3). when wp is high, the lock-down function of the bpl bit is disabled. table3: conditions to execute write-status- register (wrsr) instruction wp bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 8/32 status register the software status register prov ides status on whether the flash memory array is available for any read or write operation, whether the device is write enabl ed, and the state of the memory write protection. during an inter nal erase or program operation, the status register may be read only to determine the completion of an operation in progress. table 4 describes the function of each bit in the software status register. table 4: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0 r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0 r 2 bp0 indicate current level of block write protection (see table 5) 1 r/w 3 bp1 indicate current level of block write protection (see table 5) 1 r/w 4 bp2 indicate current level of block write protection (see table 5) 1 r/w 5 reserved reserved for future use 0 n/a 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0 r 7 bpl 1 = bp2,bp1,bp0 are read-only bits 0 = bp2,bp1,bp0 are read/writable 0 r/w note1 : only bp0,bp1,bp2 and bpl are writable note2 : all register bits are volatility note3 : all area are protected at power-on (bp2=bp1=bp0=1) busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for t he next valid operation. write enable latch (wel) the write-enable-latch bit indicate s the status of the internal memory write enable latch. if the write-enable-latch bit is set to ?1?, it indicates the device is wr ite enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any memory write (program/ erase) commands. the write-enable-latch bit is autom atically reset under the following conditions: ? power-up ? write-disable (wrdi) instruction completion ? byte-program instruction completion ? auto address increment ( aai) programming reached its highest memory address ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-status-register instructions
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 9/32 instructions instructions are used to read, write (erase and program), and configure the f25l004a. the instru ction bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any byte-program, auto address increment (aai) programming, sector-erase, block-erase, or chip-erase instructions, the write-enable (wren) instruction must be executed first. the complete list of the instructions is provided in table 5. all instructions are synchronized off a high to low transition of ce . inputs will be accepted on the rising edge of sck starting with the most significant bit. ce must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id and read-status-register in structions). any low to high transition on ce , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. instruction commands (op code), addresses, and data are all input from the most signi ficant bit (msb) first table 5: device operation instructions bus cycle 1 2 3 4 5 6 cycle type/ operation 1,2 max freq s in s out s in s out s in s out s in s out s in s out s in s out read 33 mhz 03h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x d out high-speed-read 0bh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x x x d out sector-erase 4,5 (4k byte) 20h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - block-erase (64k byte) d8h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z - - - - chip-erase 6 60h c7h hi-z - - - - - - - - - - byte-program 5 02h hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in hi-z - - auto-address-increment-word programming (aai) adh hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z d in 0 hi-z d in 1 hi-z read-status-register ( rdsr ) 05h hi-z x d out - note 7 - note 7 - note 7 -- enable-write-status-register ( ewsr ) 8 50h hi-z - - - - - - - - - - write-status-register ( wrsr ) 8 01h hi-z data hi-z - - -. - - - - - write-enable ( wren ) 11 06h hi-z - - - - - - - - - - write-disable ( wrdi ) 04h hi-z - - - - - - - - - - read-electronic-signature ( res ) abh hi-z x 12h - - - - - - - - 20h(top) jedec-read-id ( jedec-id ) 10 9fh hi-z x 8ch x 21h(bottom) x 13h - - - - 90h (a0=0) 8ch 12h read-id ( rdid ) 90h (a0=1) hi-z a 23 -a 16 hi-z a 15 -a 8 hi-z a 7 -a 0 hi-z x 12h x 8ch enable so to output ry/by# status during aai ( ebsy ) 70h hi-z - - - - - - - - disable so to output ry/by# status during aai ( dbsy ) 50 mhz 100 mhz 80h hi-z - - - - - - - - 1. operation: s in = serial in, s out = serial out 2. x = dummy input cycles (v il or v ih ); - = non-applicable cycles (cycles are not necessary) 3. one bus cycle is eight clock periods. 4. sector addresses: use ams- a12, remaining addresses can be v il or v ih 5. prior to any byte-program, sector-erase, block-erase,or ch ip-erase operation, the write-enab le (wren) instruction must be executed. 6. to continue programming to the next se quential address location, enter the 8-bit command, adh, followed by the data to be programmed. 7. the read-status-register is continuo us with ongoing clock cycles until terminated by a low to high transition on ce . 8. the enable-write-status-register (ewsr) instruction and the write-stat us-register (wrsr) instruction must work in conjunctio n of each other. the wrsr instruction must be executed immediately (very next bus cycle) after the ewsr instruction to make both instructions effective. 9. the read-electronic-signature is contin uous with on going clock cycles until terminated by a low to high transition on ce . 10. the jedec-read-id is output first byte 8ch as manufacture id ; second byte 20h as top memory type and second byte 21h as
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 10/32 bottom memory type ; third byte 13h as memory capacity. 11. the write-enable (wren) instruction and the write-status-register (wrsr) instructio n must work in conjunction of each other . the wrsr instruction must be executed imm ediately (very next bus cycle) after the wr en instruction to ma ke both instructions effective. both ewsr and wren can enable wrsr, user just nee d to execute one of it. a successful wrsr can reset wren. read (33 mhz) the read instruction supports up to 33 mhz, it outputs the data starting from the specified a ddress location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address spac e, i.e. for 4mbit density, once the data from address location 7ffffh had been read, the next output will be from address location 00000h. the read instruction is initiat ed by executing an 8-bit command, 03h, followed by address bits [a 23 -a 0 ]. ce must remain active low for the duration of the read cycle. see figure 2 for the read sequence. figure 2 : read sequence ce sck si 1 2 3 4 5 6 7 8 15 16 23 24 31 3 2 39 40 47 48 55 56 63 64 70 n+ 4 d ou t n+3 d out n+2 d out n+1 d out n d out msb msb msb high impenance so 03 mode3 mode1 add. add. add.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 11/32 fast-read (50 mhz ; 100 mhz) the high-speed-read instruction supporting up to 100 mhz is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce must remain active low for the duration of the high- speed-read cycle. see figure 3 for the high-speed-read sequence. following a dummy byte (8 clocks input dummy cycle), the high-speed-read instruction output s the data starting from the specified address location. the dat a output stream is continuous through all addresses until terminated by a low to high transition on ce . the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4mbit dens ity, once the data from address location 7ffffh has been read, t he next output will be from address location 000000h. figure 3 : high-speed-read sequence ce sck si 0 1 2 3 4 5 6 7 8 1516 2324 3132 39 40 4748 55 56 6 3 64 80 n+ 4 d ou t n+ 3 d ou t n+2 d out n+1 d out n d ou t msb msb msb high impenance so 0b add. add. a dd . mod e3 mode0 71 72 x no te : x = dummy byte : 8 clocks input dummy (v il or v ih )
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 12/32 byte-program the byte-program instruction pr ograms the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a progr am operation. a byte-program instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce must remain active low for the duration of the byte-program instruction. the byte-program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce must be driven high before the instructi on is executed. the user may poll the busy bit in the software stat us register or wait tbp for the completion of the internal self -timed byte-program operation. see figure 4 for the byte-program sequence. figure 4 : byte-program sequence ce sck si 012345678 1516 2324 3132 39 lsb msb msb high impenance s o 02 a dd. add. a dd. mod e3 mode0 d in msb
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 13/32 auto address increment (aai) word program the aai program instruction allows multiple bytes of data to be programmed without re-i ssuing the next sequential address locat ion. this feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. an aai progra m instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) w hen initiating an aai program instruction. wh ile within aai word programming sequence, t he only valid instructions are aai word program operation, rdsr, wrdi. users have three options to determine the completion of each aai word progr am cycle: hardware detection by reading the so; software detection by polling the busy in the software status register or wait t bp . refer to end-of-write detection section for details. prior to any write operation, the write-enab le (wren) instruction must be executed. t he aai word program instruction is initiat ed by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two byte s of data is input sequentially. the data is input sequentially from msb (bit 7) to lsb (bit 0) . the first byte of data(do) will be programmed into the initial address [a 23 -a 1 ] with a 0 =0; the second byte of data(d1) will be programmed into the initial address [a 23 -a 1 ] with a 0 =1. ce must be driven high before the aai word program instruction is executed. the us er must check the busy status before entering t he next valid command. once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. wh en the last desired byte had been entered, c heck the busy status using the hardware met hod or the rdsr instruction and execute the wrdi instruction, to terminate aai. user mu st check busy status after wrdi to determi ne if the device is ready for any command. please refer to figures 7 and figures 8. there is no wrap mode during aai programming; once the highest unpr otected memory address is reac hed, the device will exit aai operation and reset the write-enable-latch bi t (wel = 0) and the aai bit (aai=0). end of write detection there are three methods to determine completion of a progra m cycle during aai word programming: hardware detection by reading the so, software detection by polling the busy bit in the software status register or wait t bp. the hardware end of write detection method is described in the section below. hardware end of write detection the hardware end of write detection method elim inates the overhead of pollin g the busy bit in the software status register duri ng an aai word program operation. the 8bit command, 70h, configures the so to indicate flash busy status during aai word programming (refer to figure5). the 8bit command, 70h, must be exec uted prior to executing an aai word program instruction. onc e an internal programming operation begins, asserting ce will immediately drive the st atus of the internal flash status on the so pin. a ?0? indicates the device is busy ; a ?1? indicates the dev ice is ready for the next instruction. de-asserting ce will return the so pin to tri-state. the 8bit command, 80h,disables t he so pin to output busy status during aai word program operation and return so pin to output software register data during aai word programming (refer to figure6). figure 5 : enable so as hardware by / ry figure 6 : disable so as hardware by / ry during aai programming during aai programming
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 14/32 figure 7 : auto address increment (aai) word-program sequence with hardware end-of-write detetion figure 8 : auto address increment (aai) word-program sequence with software end-of-write detetion
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 15/32 64k-byte block-erase the 64k byte block-erase instruction clears all bits in the selected block to ffh. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (w ren) instruction must be executed. ce must remain active low for the duration of the any command sequence. the block-eras e instruction is initiated by executing an 8-bit command, d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms = most significant address) are used to determine the block address (ba x ), remaining address bits can be vil or vih. ce must be driven high before the instruction is executed. the us er may poll the busy bit in the software status register or wait tbe for the completion of the internal self-timed block-eras e cycle. see figure 9 for the block-erase sequence. figure 9 : 64-kbyte block-erase sequence
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 16/32 4k-byte-sector-erase the sector-erase instruction clears all bits in the selected sector to ffh. a sector-erase instru ction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) inst ruction must be executed. ce must remain active low for the duration of the any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be vil or vih. ce must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait tse for the completion of the internal self-timed sector-erase cycle. see figure 10 for the sector-erase sequence. ce sck si 012345678 15 16 23 24 31 msb msb high impenance so 20 add. add. add. mode3 mode0 figure 10 : sequence-erase sequence
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 17/32 chip-erase the chip-erase instruction clears all bits in the device to ffh. a chip-erase instruction will be igno red if any of the memory area is protected. prior to any wr ite operation, t he write-enable (wren) instruction must be executed. ce must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce must be driven high bef ore the instruction is executed. the user may poll the bu sy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 11 for the chip-erase sequence. figure 11 : chip-erase sequence read-status-register (rdsr) the read-status-register (rdsr) instruction allows reading of the status register. t he status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce must be driven low before the rdsr instruction is entered and remain low until the status data is read. read-status-register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the ce see figure 12 for the rdsr instruction sequence. figure12 : read-status-register (rdsr) sequence ce sck si 0123456789 bit7 msb msb high impenance so 05 mode3 mode1 10 11 12 13 14 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status register out ce sck si 01234567 msb hi gh impenan ce so 60 or c7 mod e3 mode0
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 18/32 write-enable (wren) the write-enable (wren) instruction sets the write- enable-latch bit to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) operation. ce must be driven high before the wren instruction is executed. figure 13 : write enable (wren) sequence write-disable (wrdi) the write-disable (wrdi) instruction resets the write-enable-latch bit and aai bit to 0 disabling any new write operations from occurring. ce must be driven high before t he wrdi instruction is executed. figure 14 : write disable (wrdi) sequence ce sck si 01234567 msb hi gh im penan ce so 06 mod e3 mode0 ce sck si 01234567 msb hi gh im penan ce so 04 mod e3 mode0
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 19/32 enable-write-status-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) in struction and opens the status register for alteration. the enable-write-status-register instruction does not have any effect and will be wasted, if it is not followed immediately by the wr ite-status-register (wrsr) instruction. ce must be driven low before the ewsr instruction is entered and must be driven hi gh before the ewsr instruction is executed. write-status-register (wrsr) the write-status-register instruct ion writes new values to the bp2, bp1, bp0, and bpl bits of the status register. ce must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see fi gure 15 for ewsr or wren and wrsr instruction sequences. executing the write-st atus-register instruction will be ignored when wp is low and bpl bit is set to ?1?. when the wp is low, the bpl bit can only be set from ?0? to ?1? to lockdown the status register, but cannot be reset from ?1? to ?0?. when wp is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, bp1,and bp2 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp pin is driven high (v ih ) prior to the low-to-high transition of the ce pin at the end of the wrsr inst ruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0 ;bp1 and bp2 bits at the same time. see table 3 for a summary description of wp and bpl functions. figure 15 : enable-write-status-register (ewsr) or writ e-enable(wren) and write-status-register (wrsr) ce sck si 01234567 msb msb high impenance so 50 or 06 mod e3 mode0 012345678910 11 12 13 1415 status register in 01 7 6 5 4 3 2 1 0
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 20/32 electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or cond itions greater than those defined in the operatio nal sections of this data sheet is not impli ed. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to vdd+0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . -2.0v to vdd+2.0v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second . no more than one output shorted at a time. ac conditions of test input rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 5 ns output load . . . . . . . . . . . . . . . . . . . . . . . . c l = 15 pf for R 75mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .c l = 30 pf for Q 50mhz see figures 19 and 20 table 6: dc operating characteristics v dd = 2.7-3.6v ; ta=0~70oc limits symbol parameter min max units test conditions i ddr read current 15 ma ce =0.1 v dd /0.9 v dd @33 mhz, so=open i ddw program and erase current 40 ma ce =v dd i sb standby current 75 a ce =v dd , vin=v dd or v ss i li i lo input leakage current output leakage current 1 1 a a v in =gnd to v dd , v dd =v dd max v out =gnd to v dd , v dd =v dd max v il v ih input low voltage input high voltage 0.7 v dd 0.8 v v v dd =v dd min v dd =v dd max v ol v oh output low voltage output high voltage v dd -0.2 0.2 v v i ol =100 a, v dd =v dd min i oh =-100 a, v dd =v dd min table 7 : recommended system power-up timings symbol parameter minimum units t pu-read 1 v dd min to read operation 10 s t pu-write 1 v dd min to write operation 10 s 1. this parameter is measured only for in itial qualification and after a design or pr ocess change that could affect this parame ter. table 8: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf 1. this parameter is measured only for in itial qualification and after a design or proc ess change that could affect this parame ter.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 21/32 read-electronic-signature (res) the res instruction can be used to read the 8-bit electronic si gnature of the device on the so pi n. the res instruction can pro vide access to the electronic signature of the device (except while an erase, program or wrsr cycle is in progress), any ers instruc tion executed while an erase, program or wrsr cycle is in prog ress is no decoded, and has no effect on the cycle in progress. figure 16 : read-electronic-signature (res) ce sck si 0123456789 bit7 msb msb high impenance so ab mode3 mode1 10 11 12 13 14 bit6 bit5 bit4 bit3 bit2 bit1 bit0 status register out
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 22/32 jedec read-id the jedec read-id instruction identifies t he device as f25l004a and the manufacturer as esmt. the device information can be rea d from executing the 8-bit command,.9fh. following the jedec read-id instruction, the 8-bit manufact urer?s id, 8ch, is output fro m the device. after that, a 16-bit device id is sh ifted out on the so pin. byt e1, bfh, identifies the manuf acturer as esmt. byte2, 20 h (for top), 21h (for bottom),identifies the memory type as spi flash. byte3, 13h, identifies the device as f25l004a. the instruction sequen ce is shown in figure17. the jedec read id instruction is terminated by a low to high transition on ce at any time during data output. if no other command is issued after executing the jedec read-id instruction, issue a 00h (nop) command before going into standby mode ( ce =v ih ). figure 17 : jedec read id sequence table 9 : jedec read-id data device id manufacturer?s id memory type memory capacity byte1 byte 2 byte 3 20h (for top) 8ch 21h (for bottom) 13h ce sck si 0123456789 high impenance so 9f mod e3 mode0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 8c 20 or 21 13 msb msb
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 23/32 read-id (rdid) the read-id instruction (rdid) identifies th e devices as f25l004a and manufacturer as esmt. this command is backward compatible to all esmt spi devices and should be used as default device iden tification when multiple versions of esmt spi devices are used in one design. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manu facturer?s id is located in address 0000 0h and the device id is located in address 0 0001h. once the device is in read-id mode, the manufacturer?s and device id output data toggles between address 00000h and 00001h unti l terminated by a low to high transition on ce . figure 18 : read-electronic-signature table 10 : jedec read-id data address byte1 byte2 manufacturer?s id 00000h 8ch 12h device id esmt f25l004a 00001h 12h 8ch
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 24/32 table 11: reliability characteristics symbol parameter minimum spec ification units test method n end 1 endurance 100,000 cycles jedec standard a117 t dr 1 data retention 10 years jedec standard a103 i lth 1 latch up 100 + idd ma jedec standard 78 1. this parameter is measured only for in itial qualification and after a design or pr ocess change that could affect this parame ter. table 12 : ac operating characteristics t a= 0~70 o c normal 33mhz fast 50 mhz fast 100 mhz vdd=2.7~3.6v vdd=2.7~ 3.6v vdd=3.0~3.6v symbol parameter min max min max min max units f clk serial clock frequency 33 50 100 mhz t sckh serial clock high time 13 9 5 ns t sckl serial clock low time 13 9 5 ns t ces 1 ce active setup time 5 5 5 ns t ceh 1 ce active hold time 5 5 5 ns t chs 1 ce not active setup time 5 5 5 ns t chh 1 ce not active hold time 5 5 5 ns t cph ce high time 100 100 100 ns t chz ce high to high-z output 9 9 9 ns t clz sck low to low-z output 0 0 0 ns t ds data in setup time 3 3 3 ns t dh data in hold time 3 3 3 ns t hls hold low setup time 5 5 5 ns t hhs hold high setup time 5 5 5 ns t hlh hold low hold time 5 5 5 ns t hhh hold high hold time 5 5 5 ns t hz hold low to high-z output 9 9 9 ns t lz hold high to low-z output 9 9 9 ns t oh output hold from sck change 0 0 0 ns t v output valid from sck 12 8 7 ns 1. relative to sck.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 25/32 erase and programming performance limits parameter typ.(2) max.(3) unit sector erase time 60 120 ms block erase time 1 2 s chip erase time 4 30 s byte programming time 7 30 us chip programming time 12 100 s erase/program cycles (1) 100,000 - cycles data retention 20 - years notes: 1.not 100% tested, excludes extern al system level over head. 2.typical values measured at 25c, 3v. 3.maximum values measured at 85c, 2.7v.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 26/32 figure 19: serial input timing diagram figure 20: serial output timing diagram
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 27/32 figure 21: hold timing diagram figure 22: power-up timing diagram
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 28/32 figure 23 : ac input/output reference waveforms figure 24: a test load example input timing re f erence le v el output timing reference level 0.8vcc 0. 2vcc 0. 7v cc 0. 3vcc 0. 5v cc ac measurement level no te : i n p ut p ulse rise an d f all time are <5ns
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 29/32 packaging diagrams 8-lead sop ( 150 mil ) b e 0 l detail "x" a a1 seating plane d a2 l1 "x" c 1 4 e h 85 0.25 gauge plane dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a 1.35 1.60 1.75 0.053 0.063 0.069 d 4.80 4.90 5.00 0.189 0.193 0.197 a 1 0.10 0.15 0.25 0.004 0. 006 0.010 e 3.80 3.90 4.00 0.150 0.154 0.157 a 2 1.25 1.45 1.55 0.049 0. 057 0.061 l 0.40 0.66 1.27 0.016 0.026 0.050 b 0.33 0.406 0.51 0.013 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.203 0.25 0.0075 0.008 0.010 l 1 1.00 1.05 1.10 0.039 0.041 0.043 h 5.80 6.00 6.20 0.228 0.236 0.244 0 --- 8 0 --- 8 controlling dimension : millimenter
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 30/32 packing dimensions 8-lead sop ( 200 mil ) a1 a2 seating plane d b e e 1 4 8 5 detail "x" l1 l a e1 dimension in mm dimension in inch dimension in mm dimension in inch symbol min norm max min norm max symbol min norm max min norm max a --- --- 2.16 --- --- 0.085 e 7.70 7.90 8.10 0.303 0.311 0.319 a 1 0.05 0.15 0.25 0.002 0.006 0.010 e 1 5.18 5.28 5.38 0.204 0.208 0.212 a 2 1.70 1.80 1.91 0.067 0. 071 0.075 l 0.50 0.65 0.80 0.020 0.026 0.032 b 0.36 0.41 0.51 0.014 0.016 0.020 e 1.27 bsc 0.050 bsc c 0.19 0.20 0.25 0.007 0.008 0.010 l 1 1.27 1.37 1.47 0.050 0.054 0.058 d 5.13 5.23 5.33 0.202 0.206 0.210 0 --- 8 0 --- 8 controlling dimension : millimenter
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 31/32 packing dimensions 8-leads p-dip ( 300 mil ) 14 85 d e 1 e e b a a 12 a seating plane e b b 1 l 0 dimension in mm dimension in inch symbol min norm max min norm max a 5.00 0.21 a 1 0.38 0.015 a 2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 bsc. 0.300 bsc. e 1 6.22 6.35 6.48 0.245 0.250 0.255 l 9.02 9.27 10.16 0.115 0.130 0.150 e 2.54 typ. 0.100 typ. e b 8.51 9.02 9.53 0.335 0.355 0.375 b 0.46 typ. 0.018 typ. b 1 1.52 typ. 0.060 typ. o 0 o 7 o 15 o 0 o 7 o 15 o controlling dimension : inch.
esmt f25l004a elite semiconductor memory technology inc. publication date : apr. 2007 revision : 1.2 32/32 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this docum ent are believed to be accurate at the time of publication. esmt assu mes no responsibilit y for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of o ur products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third part ies which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other inte llectual property rights of esmt or others. any semiconductor devices may have i nherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards agains t injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt 's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of applicatio n, purchaser must do its own quality assurance testing appropriate to such applications.

▲Up To Search▲

Price & Availability of F25L004A-100PG

	To Download F25L004A-100PG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .